Top Project Status (10/03/2011 - 22:38:45) | |||
Project File: | XTideCPLD1_XC9572XL_v2.xise | Parser Errors: | No Errors |
Module Name: | Top | Implementation State: | Fitted |
Target Device: | xc9572xl-10TQ100 |
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No Errors |
Product Version: | ISE 13.2 |
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9 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | za 11. feb 16:12:45 2012 | 0 | 9 Warnings (0 new) | 0 | |
Translation Report | Current | za 11. feb 16:12:53 2012 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Current | za 11. feb 16:13:00 2012 | 0 | 12 Warnings (1 new) | 3 Infos (3 new) | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Fit Simulation Model Report |