Top Project Status (10/03/2011 - 22:38:45)
Project File: XTideCPLD1_XC9572XL_v2.xise Parser Errors: No Errors
Module Name: Top Implementation State: Fitted
Target Device: xc9572xl-10TQ100
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
9 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentza 11. feb 16:12:45 201209 Warnings (0 new)0
Translation ReportCurrentza 11. feb 16:12:53 2012000
CPLD Fitter Report (Text)Currentza 11. feb 16:13:00 2012012 Warnings (1 new)3 Infos (3 new)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 02/11/2012 - 17:00:25