Top Project Status
Project File: XTideCPLD1_XC9536XL_3.3V_v1a.xise Parser Errors: No Errors
Module Name: Top Implementation State: Fitted
Target Device: xc9536xl-10VQ44
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
13 Warnings (13 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentwo 17. aug 19:31:17 2011013 Warnings (13 new)0
Translation ReportCurrentwo 17. aug 19:31:24 2011000
CPLD Fitter Report (Text)Currentwo 17. aug 19:31:27 201103 Warnings (3 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 08/17/2011 - 19:41:49