MiSTer FPGA Forum

andrezheng

I've found this in the log file when blamk screen happens. Why the i2c bus can't be found? Is this i2c related to SOC<->ADV7513 or ADV7513 <-> HDMI Monitor? Anybody knows this? Thanks INI_PARSER : Opened file yc.txt with size 7680 bytes. INI_PARSER : Got yc_mode 'JTCPS1_59.6' with VALUE 40997539300 INI_PARSER : Got yc_mode 'JTCPS15_59.6' with VALU...

andrezheng

I've found this in the log file when blamk screen happens. Why the i2c bus can't be found? Is this i2c related to SOC<->ADV7513 or ADV7513 <-> HDMI Monitor? Anybody knows this? Thanks INI_PARSER : Opened file yc.txt with size 7680 bytes. INI_PARSER : Got yc_mode 'JTCPS1_59.6' with VALUE 40997539300 INI_PARSER : Got yc_mode 'JTCPS15_59.6' with VALUE...

andrezheng

Update
Failed with below tests, Still periodically blanks:
(1)vsync_adjust = 0
(2)vsync_adjust = 1
(3)vsync_adjust = 2
(4)Installed 128 SDRAM module correctly
(5)Use different 5V power supplys

andrezheng

AngelicLiver wrote: ↑Wed Oct 11, 2023 12:50 pm
The main menu does not need SDRAM but installed incorrectly it can cause issues (or even damage the DE10-Nano). I've seen power supplies with insufficient amperage causing problems like this too.

Thanks again. I'll check all the three things you mentioned.

andrezheng

Power supply is using the one in the DE10-nano kit.

andrezheng

What is vsync_adjust set to in your MiSTer.ini and which power supply are you using? [edit] I've also noticed the memory icon is indicating that no SDRAM module is installed, you might want to check it is installed correctly. Thanks for your explanation. The vsync_adjust is set to 0. And yes, the SDRAM module is actually installed but not detected...

andrezheng

128M SDRAM module installed on GPIO_0
Please help check the attached video.
Thanks

andrezheng

谢谢各位的努力！明年再接再厉！

andrezheng

Is it possible to add an TFT LCD, like 4.3 inch LCD to make Mister portable.............

andrezheng

Great idea. BTW, where can you get the 5CSEBA6 at a reasonable price?

andrezheng

issue closed. Soldering problem.

andrezheng

Hello, The U-Boot tells the below info. Has anyone met same issue? Does it mean the FPGA need encrypted configuration file or something else? socfpga_bridges_reset: FPGA not ready, aborting And also, the PL part can not also be detected by the Quartus II/Programmer. And the HPS core could be detected by the QUartus II/Programmer. Thanks for sharing...

andrezheng

:D Today, I successfully powered up the newly designed 5CSEBA6U23 core board. And the new core board's top and bottom images are attached. Two AS4C32M16SBs, 1GB DDR3 memory, RGMII ETH PHY and 85 FPGA GPIOs from PL side.... Now I'm thinking of design a daughter board for this core board. Preliminary, below interfaces will be added: (1)ADV7513 HDMI d...

andrezheng

The IOs in the expansion headers are 3.3V LVTTL. Not compatible to the DDR voltage level.

andrezheng

5CSEBA6U23 costs around $200. That's why want to throw the De-10 Nano away. In replacement, I'll spend $15 to buy a Raspberry Pi Zero W or another ARM chip with Linux system. And spend less than $100 for Cyclone V 5CEFA7F23(150K LE) or Xilinx XC7A200T. After I comment these two variables, the Mister Main can running on Raspberry Pi now. pi@raspberr...

andrezheng

Hi everyone, I'm trying to port the Main_MiSTer project to other ARM core(Raspberry Pi Zero W). I met some compile issue for below two variables in video.cpp. extern uint8_t _binary_logo_png_start[], _binary_logo_png_end[]; I searched all the project files and found nothing. Could anyone please help tell me where are these two variables located? Wh...

andrezheng

I will go on with Cyclone V directly instead of the Exor module. The first important and most difficult step after the creation of the FPGA component will be to do the DDR3 routing with KiCad. Now we will have to be patient, the next tens of hours may be concentrated on this part of the layout !! Luckily the new features of kicad 6 are really prom...

andrezheng

Reed_Solomon wrote: ↑Tue Dec 22, 2020 6:01 am The only benefit I can see would be if it was designed to fit in a portable case with LCD.

Another important thing is JT seems meet some issue related the clock speed for SDRAM when porting CPS1.5. If the SDRAM modules merged into the core board, then the SDRAM's performance will be much better.

andrezheng

I'll switch to draw a core board first. This seems take much less effort.

andrezheng

breiztiger wrote: ↑Sun Dec 13, 2020 1:19 pm nice work !!!

you do think to sell this ?

My purpose of designing this daughter board is to verify the components' package dimension. This is some kind of preparation work for my final design with Cyclone V SoC.

andrezheng

Verified my all in one board. The SDRAM BOARD: AS4C32M16SB-7TCN, I/O, USB hub by using Microchip USB2514.

andrezheng

Put the USB hub, SDRAM, VGA/Audio board into one main board?

The layout makes me so exhausted.............

andrezheng

:D :D :D Thank you so much for your detailed explain. I'll digest these comments one by one. :) C6 appears to AC couple the green signal, likely to provide DC isolation between it and the sync signals. R2 drops VSync to an appropriate level for Q1's base. Q1 appears to modulate the HSync signal with the VSync signal, to create a composite sync sign...

andrezheng

Hi Guys

Could you please let me know why the VGA display port designed in this way?
(1) Why there's an capacitor C6 on the G color line?
(2) What is the functionality of the circuit highlighted in red rectangle? R1, R2, Q1, SOG?

Thank you so much.

andrezheng

Is xilinx xc7z030 a good candidate or not? 800MHz cpu, 125K LEs... and the price is around 60$.

andrezheng

Just checked the schematic, this 96 board is useless for Mister fpga since all the IOs extended to the connectors are HPS IOs. Not possible to put SDRAM addon on this board.

andrezheng

I just ordered two Chameleon96 boards. Let's wait and to see what I am going to get.

andrezheng

For the SDRAM add on, why DQMH and DQML connected to A11 and A12?
Tell me why. Ain’t nothing but a mistake??

andrezheng

Ok. My mistake. The board costs $130.

andrezheng

The cheapest price for this SoC 5CSEBA6U23I7N, I can get from some china local vendor is around 100$. And this chip is not in stock and the lead time is very long. So at this point, it is still not a good point to redesign the DE10-Nano now.

MiSTer FPGA Forum

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