Primeira_Fase wrote: ↑Sat Mar 16, 2024 6:57 amIt seems like these guys found a solution to the latency issue in DDR3 on another FPGA board, but it's DDR3 memory as well.
Look the logs.
According to Robert, the difference/issue on the MiSTer/De10-nano is that the DDR3 is shared between FPGA and linux on the HPS-side.