MiSTer FPGA Forum

Well, putting that qemu issue aside (reported to qemu mailing list) it other runs 'as before' in qemu 6.2.0.

I see the kernel has been updated again, I'd better update the modules too.

Then we're at least back to where it was before

Looks to be this revision... I'll see if I can understand why. git bisect bad fa947a667fceab02f9f85fc99f54aebcc9ae6b51 is the first bad commit commit fa947a667fceab02f9f85fc99f54aebcc9ae6b51 Author: Richard Henderson <richard.henderson@linaro.org> Date: Thu Jul 29 10:45:10 2021 -1000 hw/core: Make do_unaligned_access noreturn While we may have had ...

I've just been trying out newer qemu. qemu 6.1.1 works fine, but 6.2.0 fails with an alignment trap. They seem to have made a fair number of changes for the Mac M1 so perhaps its a regression related to that, trying to find out.

The kernel module is working now on the latest mister (5.14.5)

I've uploaded the latest kernel module and also the latest qemu (6.10) here:
http://www.64kib.com/mister_hybrid_files/

This is all just getting it up to date and reminding myself where I'm up to, no fixes at this point.

Managed to work around by using an explicit interrupt-parent, it complains then works!

Still struggling to make this work. The .dts override I had before no longer works. I did manage to apply it but seems to be an issue with how the references work. So I need to reference intc, previous I added an intc block. That needs to no longer work and the right was is to using /plugin/;. However that fails to find intc when I apply the overla...

Looks like I need the module linked here:
https://stackoverflow.com/questions/508 ... e-overlays

Found the solution I think: Need another module now since its not in mainline.
https://stackoverflow.com/questions/508 ... e-overlays
I'll include it in the release.

I got the mister upgraded to linux 5 and rebuilt the kernel module ok. Though the device tree overlays no longer seem to exist, so trying to work out how to apply them them!

Hi,

I was applying a device tree overlay in kernel 4.19 by mounting configfs, upon which I'd see the device-tree. After upgrading to 5.14 I no longer see this, does anyone know how to do the same thing in 5.14?

Is there a new system to provide configuration to custom modules in Linux 5?

Thanks,

Mark

Regarding mister updates: Probably just the kernel module will need recompiling. I should update my mister and try.

It was plain old vanilla musashi from head on GitHub. I also tried the pistorm version in case there were significant patches. The mister side was a custom main which uses mmap to map the registers in etc. I think I posted it. Now its getting colder again, be good to start on this again. Though I really don't want to do that without someone with se...

Oh well, then back to plan A
* increase clock
* pipeline failing paths
* repeat!

Guess that quote was more suitable for a https://en.wikipedia.org/wiki/Load–store_architecture. Though it is still a good interview.

I did try the musashi from pistorm earlier in the thread, are there are more recent changes?

I should upload my last changes to the kernel module and stuff.

While I've been doing other projects, has anyone been trying to improve this? I'll be back to it in a few weeks I reckon.

Just watching this great interview with Jim Keller. One good quote is that 80% of the execution is ~6 instructions:load, store, add, subtract, compare and branch.

Perhaps we can clock TG68K and the cache say 4x faster then add a 4 cycle pipeline for all the other instructions.

https://www.youtube.com/watch?v=AFVDZeg4RVY

I built it with Quartus 17 and ... it didn't work. Then I went back to the core that worked before and it stopped working! So not sure what is going on, perhaps related to using VGA instead of HDMI. I'll plug in my HDMI monitor next time I take a look (probably a couple of weeks, busy with other stuff...).

So rtg... With the official 20210305 it works. With my own unmodified build it failed. So perhaps the git code was bad for a few days, trying a clean version. Confirmed that RTG doesn't work on a clean checkout. Perhaps because I'm using Quartus 20.1.1. So something else to look into before I try the hybrid one. Actually I realize that I have 17.0...

So rtg... With the official 20210305 it works. With my own unmodified build it failed. So perhaps the git code was bad for a few days, trying a clean version.

Interesting. This is an advantage we have in the fpga, we can snoop Amiga dma writes. On Amiga it sounds like data cache is disabled on chip ram - according to Gunnar here: http://www.apollo-core.com/knowledge.php?b=4&note=2795&z=-AGF3K We already effectively have instruction cache since qemu compiles the instructions and caches them. So......

robinsonb5 wrote: ↑Fri May 21, 2021 8:23 pm Remember that the CPU isn't the only thing that writes to chip RAM - you're going to need some kind of bus snooping if you want to cache chip RAM.

Wouldn’t this be the case on the original hardware? So the cpu is unaware that chip ram has changed and the software has to handle it?

I guess there is a cache inhibit signal for hardware regs.

qemu seems to have some cache flushing logic in the core. However I don't see any cache action taken on cacr changes or CINV,CPUSH. I guess the latter aren't used much on the Amiga anyway since its only 68040+.

So I took a look at the mmuhack. It was armv6 based and the cortex v9 is arm7. I found this, which dumps the armv7 page tables. (I had to add it to the kernel module since it needs supervisor mode) https://github.com/yifanlu/ARMv7_MMU_Dumper Anyway I ended up using the kernel api. Its easy to add mmap to fops (for debugfs need to use debugfs_create...

Could also try the hybrid stuff that I'm playing with on the Amiga core, let me know when you get to that point (if interested).

edit: errr, saw you already mentioned that in the first post

The control regs are in that region too?

Remembered there was a solution for this on gp2x.

mmuhack kernel module here (by squidge, modified by notaz)
https://notaz.gp2x.de/dev.php

Perhaps this can be adapted.

Right, so to get that working again need to work out how to enable the caching. in uboot we pass these kernel options mem=511M memmap=513M$511M i.e. use 511M and restart 513M. When I started I was mmaping the 384MB fast from the 513MB region. Even though I didn't use O_SYNC on the open it seemed uncached. Pass we can pass mem=1024M and tell the ker...

foft wrote: ↑Tue May 18, 2021 9:05 pm What is the memory map for rtg? I’d like to get that working properly with this.

Is it just in Z3 fast ram? So if I fix the caching and start using the 'correct' DDR3 area again rather than malloc'ed ram will RTG work again?

What is the memory map for rtg? I’d like to get that working properly with this.

I just installed stackatack2 'as-is'. With my simple loop it worked every time (of about 5-6 tries) now. I tried (real) dhrystones and get about 55000. This isn't quite the 400000 still so I wonder if something else is going on there, anyway its much much better than I got before. Anyway this seems worth improving. Though of course the issue remain...

Since it grows down any code right after the stack allocation will clash, however large it is?

Still I might install it then put an 8k variable on the stack at the start of the dhrystones program.