MiSTer FPGA Forum

Hi there, I am currently in the works of designing my own I/O board and would like to incorporate a DAC IC fed by an I2S stream to circumvent the poor analog audio of the MiSTer. At the same time, I would like to keep SPDIF functionality should I ever want to connect the MiSTer to an AVR. However, official documentation does not seem to exist or I ...

Yes, this is correct. This is the standard Altium gerber layer sequence (Sorgelig uses Altium for PCB design). A second remark regarding capacitors: Using only 1uF caps as marked in the schematic should be fine, as the regulator will do the heavy lifting regarding power supply filtering. I originally planned on putting together a v2.5 SDRAM board w...

I just made sure not to use no-name capacitors from shady sources. IIRC the caps I used are by KEMET and Vishay. I agree that getting all parts is a messy task. Also it is not entirely clear which capacitance values to use. I followed the suggestions made by MickGyver given in Post 18 of this thread: https://misterfpga.org/viewtopic.php?f=8&t=2...

Hi there, I've built one v2.9 SDRAM board using the 6TIN variety of SDRAM ICs. My board is stable at 141MHz, however I have only run the memtest core for around 30 minutes and without any active cooling. It seems that signal quality is the limiting factor.