I have read it is possible to set aside an amount of the DDR3 while reducing the total for the ARM -- say a 64Mb chunk for the FPGA. At what point could one expect memory latency issues with the FPGA using the DDR3?
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The original 99/4A actually had four wait states implemented as the 16-bit data bus was converted into an 8-bit one. So, it was not really running as fast as it could. The only onboard RAM was a 128 x 16 byte static RAM.
Respectfully,
James