MiSTer Core Dev Episode 10: 6502 Verilog

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nico24
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MiSTer Core Dev Episode 10: 6502 Verilog

Unread post by nico24 »

A look at how to implement a 6502 CPU in Verilog for use in MiSTer cores. The hardware test circuit from the last episode is simulated in Modelsim, with discussion.

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Alkadian
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Re: MiSTer Core Dev Episode 10: 6502 Verilog

Unread post by Alkadian »

Thanks a lot for this new episode!
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Re: MiSTer Core Dev Episode 10: 6502 Verilog

Unread post by breiztiger »

great

thanks
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