MiSTer FPGA Forum

Hi folks,

With the availability of new NES boards (such as nesessity) one could build a pretty much all new NES with the exception of CPU and PPU. I was wondering if it was possible (and if anyone tried) separating the NES core's CPU and PPU logic into standalone FPGA-based CPU and PPU replacement chips for projects like this.

My naive idea is that, perhaps, this could be done in two smaller and cheaper FPGAs (like Lattice). I was hoping someone better informed could comment on this and perhaps even evaluate the complexity of the project.

Cheers!

PS. I understand that this is not directly related to MiSTer, however if such project was possible, it would only make sense to base it off MiSTer core.

It has been done for a Yamaha sound chip. It uses the core developed by Jotego and the board is a tiny board which plugs right into the socket of the original chip. I think it is a Lattice FPGA and it does not need an EEPROM as it retains its programming.

Interesting, thank you for the information!

It appears that someone implemented a full NES on an ICE40 (github link), so the CPU alone or the PPU alone should be possible as well at least in theory.

It is definitely possible, it has been done for the ULA chip for Spectrums, e.g.:

http://blog.retroleum.co.uk/electronics ... nt-module/

As long the FPGA implementation of the component is pin compatible and cycle accurare, it would work.

It would be nice to have new ASICs made as drop-in replacements if that's at all feasible. The clones that already exist have known issues (mainly with sound, if I recall correctly).

If going the FPGA route, wouldn't it make more sense to design an entirely new PCB centered around a singular FPGA? That'd be the ultimate way of reviving a broken NES.