MiSTer FPGA Forum

If I am not mistaken, most SNAC boards use mosfet based bidirectional voltage level translator.
Now, I know with SNAC no conversion is done so each core must be matched with its controller.
But let's suppose a user starts a nes core with a genesis controller still plugged after running a genesis game.
In this case the nes core will try to toggle user IO 0 and 1 (clock and latch for the nes snac), but if either up or down are pressed, those lines are held low by the high side of the voltage level translator.

Now, my question is, will that damage the FPGA? Will the FPGA pin will be pulled high with consequent high current draw from the mosfet pulling low?
Or is the output pin set up to work in "open collector" fashion and does it never actively pull high, but let the pull up resistors do that work?

It’s used in open collector/open drain mode.

Reassuring to hear, thanks!

Yes, if the core uses the unmodified sys framework.

The cores by Jotego and DB9 cores have modified the framework and do pull some pins high when DB9/DB15 is selected.

Are these cores in the official repository? Or are they a fork like the ones supporting Snac8?

The Jotego cores and the DB9 cores are not part of the official repository.
But for people using the update-all script, they may not be able to easily distinguish which downloaded cores are the official ones versus unofficial...

I am one of such users, I use update_all (I do not uncomment/edit it in any way though)