MiSTer FPGA Forum

Is the method of overclocking by "adding scanlines" (or some variant of it), described in this article viable on FPGAs:

• “Blast processing” in 2019: How an SNES emulator solved overclocking

An advantage of this kind of overclocking seems to be that in most games it does not cause problems with additional bugs/unnecessary speed-ups in comparison to "normal overclocking".

See as well:

• Overclocked FCEUX Side-by-side Comparison (NES implementation)

Nobody answered you, so I will attempt that: The FPGA cores we have strive to resemble real hardware. Features like that in software emulation aren't simple to translate to FPGA logic, and since it's hard enough to get an accurate core written, extensions such as that are not really in the cards. Features like save states are simple to implement in software emulation, but much harder in FPGA logic.

You will see certain MiSTer cores do have options to help prevent slowdowns, but I can't recall seeing anything run as fast as the StarFox videos linked in that article.