Bas wrote: ↑Mon Apr 08, 2024 2:27 pm
I'll dig into the code for a bit.. If there really are things in the core that are unreachable from SYSCTL, I'll submit a PR to get that rectified. The C program looks simple enough. I'll just have to hunt for the twiddly bits in the core's code fore a bit because I don't know any HDL.
Thanks,
I took a look at the code and it appears to write a hard coded value to an I/O port (0x8888) that switches the setting. It does look like something that would need to be setup on the HDL side first and then have the code trigger the switch.
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outpw(0x8888, 0xA100 | (arg & 0xFF));
( https://github.com/MiSTer-devel/ao486_M ... SCTL.C#L71 )
I don't know much HDL but this code looked interesting:
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(* romstyle = "logic" *) wire [27:0] clk_rate[8] = '{90000000, 15000000, 30000000, 56250000, 100000000, 100000000, 100000000, 100000000 };
(* romstyle = "logic" *) wire [17:0] speed_div[8] = '{ 'h0505, 'h1e1e, 'h0f0f, 'h0808, 'h20504, 'h20504, 'h20504, 'h20504 };
( https://github.com/MiSTer-devel/ao486_M ... 86.sv#L483 )
and
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'd1: begin clk_req <= 'd3; l1 <= 1'b1; l2 <= 1'b1; end // ao486 XT 7
'd2: begin clk_req <= 'd1; l1 <= 1'b1; l2 <= 1'b0; end // ao486 AT 8
'd3: begin clk_req <= 'd2; l1 <= 1'b0; l2 <= 1'b1; end // ao486 AT 10
'd4: begin clk_req <= 'd2; l1 <= 1'b1; l2 <= 1'b0; end // ao486 AT 20
'd5: begin clk_req <= 'd1; l1 <= 1'b0; l2 <= 1'b0; end // ao486 PS/2 20
'd6: begin clk_req <= 'd3; l1 <= 1'b1; l2 <= 1'b0; end // ao486 3SX 25
'd7: begin clk_req <= 'd2; l1 <= 1'b0; l2 <= 1'b0; end // ao486 3DX 33
'd8: begin clk_req <= 'd0; l1 <= 1'b1; l2 <= 1'b0; end // ao486 3DX 40
'd9: begin clk_req <= 'd3; l1 <= 1'b0; l2 <= 1'b0; end // ao486 4SX 33
'd10: begin clk_req <= 'd0; l1 <= 1'b0; l2 <= 1'b0; end // ao486 MAX (stable)
'd11: begin clk_req <= 'd4; l1 <= 1'b0; l2 <= 1'b0; end // ao486 MAX+ (unstable)
( https://github.com/MiSTer-devel/ao486_M ... 86.sv#L440 )
From that code only 5 clock values (d0 to d4) and the l1 / l2 cache values are being used for those menu CPU Presets.. (and d4 is a special value to set it to Max), so it appears you were correct.
It just doesn't make sense with benchmark measurements as the menu CPU Presets provided different results than setting with 'SYSCTL SYS'.
